In memory circuits such as a non-volatile memory, it is necessary to generate a high voltage for performing programming or reading of data in a memory cell.
In case the high voltage is generated using a common booster circuit, a drop in a supply voltage will be brought about, when an amount of current at a time of voltage boosting exceeds supply capability of a power source. Accordingly, it becomes necessary to perform distribution of peak current.
As one of techniques for achieving this, a technique of changing a phase of a control clock signal for each charge pump in order to control a plurality of charge pump circuits has been traditionally used a lot. However, a scheme for coping with a delay in the course of generating a phase difference and simultaneous phase changes of the control clock signals at a time of starting and ending the voltage boosting becomes necessary.
Patent Document 1 discloses a configuration of a booster circuit as shown in FIG. 5, in which a peak current generated by overlapping of noise at a time of cell data amplification with noise caused by an operation of the booster circuit is distributed, thereby stabilizing the cell data amplification. Referring to FIG. 5, this booster circuit includes a voltage detection circuit 1 for detecting a boosted voltage and outputting a decision output signal φ1 that controls a boosting operation, an oscillation circuit 21 for performing oscillation upon receipt of control by the decision output signal φ1 from the voltage detection circuit 1 and outputting an output signal φ2, a plurality of control circuits 5 that receives respective output signals of the voltage detection circuit 1 and the oscillation circuit 21, for controlling charge pump circuits, and a plurality of charge pump circuits 3 that operate under the control of the control circuits 5. Each control circuit 5 includes transfer gates TG2 and TG3 for receiving the output signal φ2 of the oscillation circuit 21 and controlling transmission of an inverted signal thereof and the output signal φ2, a first latch circuit 6 for latching a signal φ3 at a connecting point between outputs of the transfer gates TG2 and TG3 for output to a charge pump circuit, a second latch circuit 7 for latching the signal φ3 through a transfer gate TG4 which is on/off controlled by the decision output signal φ1, and a circuit 8 for controlling the transfer gates TG2 and TG3 so that, out of a logic and an inverted logic of the output signal φ2 of the oscillation circuit, the logic inverted to a logic of the signal latched by the second latch circuit 7 is selected and output, based on the signal φ3 and an inverted signal φ3− (inverted output signal of the second latch circuit 7) and the decision output signal φ1 of the voltage detection circuit 1. Activation of the first latch circuit 6 is controlled by the decision output signal φ1.
FIG. 8 shows an example of a configuration of the voltage detection circuit 1. Referring to FIG. 8, the voltage detection circuit 1 has a configuration in which a potential at a voltage boosting node VB is divided by resistance, for comparison with a reference voltage VREF by a comparator COMP. When the potential at the node VB is lower than a set potential determined by a resistance division ratio and the reference voltage VREF, the decision output signal φ1, which is an output of the comparator goes high (indicating a voltage boosting operation). On the contrary, when the potential at the node VB is higher, the decision output signal φ1 goes low (indicating no voltage boosting operation).
FIG. 9 shows an example of a configuration of the charge pump circuit 3. The configuration shown in FIG. 9 is referred to as a complementary circuit system, and is controlled by a square wave of the signal φ3 in FIG. 5 (or a signal φ4 in FIG. 1). Capacitors C1 and C2 operate with opposite phases.
FIGS. 6A and 6B show a timing waveform diagram explaining an operation of the configuration shown in FIG. 5. When it is determined that the boosted voltage reaches a preset voltage at the voltage detection circuit 1 as shown in FIG. 6A, the decision output signal 11 (φ1′ and φ1″) transitions from high to low. The control signal φ3 (φ3′ and φ3″) for the charge pump circuit is held by the first latch circuit 6 and the second latch circuit 7. The charge pump circuit 3 is stopped. On the other hand, the output φ2 (φ2′ and φ2″) returns to an initial state.
When it is determined that the boosted voltage does not reach the set voltage at the voltage detection circuit 1, the decision output signal φ1 (φ1′ and φ1″) transitions from low to high. The signal φ3 (φ3′ and φ3″) is a signal obtained on switching positive and negative logics of the output signal φ2 of the oscillation circuit 21 forcefully by a level held at the second latch circuit 7. As a result, the clocking of signal φ3 (φ3′ or φ3″) starts from a negative logic of a level held at the first latch circuit 6. An operation of the charge pump circuit 3 is resumed, and the voltage boosting operation is performed.
[Patent Document 1]
JP Patent Kokai Publication No. JP-A-11-25673